As the semiconductor design and the manufacture technique update, the rate of improvement in components accelerates, and the size of panel and the resolution of TFT-LCD increase, the distortion of the gate pulse signal due to the resistance-capacitance (RC) signal delays will increase. To decrease the RC signal delays, low resistance material for the connection between the components must be chosen. As the density of the components increases, the line width of the connection will decrease to induce the electromigration problems by high current density, so that it becomes a factor in choosing the material. Generally speaking, the conventional connection material is aluminum (Al) which resistivity is about 2.66 μΩ-cm. But using copper (1.67 μΩ-cm) or silver instead of aluminum for connection material is regarded as a practicable proposal gradually because copper and silver have higher resistance-to-electromigration and lower resistivity than aluminum.
Referring to FIG. 1, a schematic view of a conventional thin film transistor is illustrated. The conventional thin film transistor comprises a substrate 11, a gate electrode 12, a gate insulating layer 13, a semiconductor layer 14, a source electrode 15, and a drain electrode 16. A gate metal is sputtered by physical vapor deposition (PVD) on the substrate 11. After patterning the gate metal by a first photolithography process to form the gate electrode 12, the gate insulating layer 13 and the semiconductor layer 14 are then sequentially deposited on the substrate 11 by Plasma Enhanced Chemical Vapor Deposition (PECVD) and patterned by a second photolithography process. Then, a second metal layer (source/drain) is sputtered and patterned by a third photolithography process to form the source electrode 15 and the drain electrode 16, wherein the source electrode 15 and the drain electrode 16 are separated by a channel region by etching. Furthermore, the conventional thin film transistor could further comprise a passivation layer and an indium-tin-oxide (ITO) layer which are then patterned by a fourth and a fifth photolithography process, respectively. As manufacturing technique varies, there are four to six steps of photolithography processes in application. This prior art is focused on the structure of the conventional thin film transistor for gist description and is ignored about the other details and principles.
In the prior art as shown in FIG. 1, after forming the gate electrode in Ag, the gate electrode may peel due to the poor adhesion of silver to the substrate, resulting a yield loss. In addition, silver sensitively reacts with chloride, sulfur and sulfide during etching process, decreasing the electrical conductivity and thermal conductivity. Silver also easily agglomerate at moderate temperature during annealing, causing an increasing resistivity of silver. In order to manufacture high quantity thin film transistor, providing a conducting wire in Ag with low resistivity and good adhesion characteristics that are a key topic that R&D staffs must solve instantly.